FIG. 1 illustrates a typical memory architecture for a single port random access memory (RAM). As shown, the architecture typically includes a "built in" column mux. One advantage of using column muxing is that each physical row of memory is equivalent to, in this case, two words rather than one word. This allows for deeper memories, i.e. total number of words, for a given physical dimension. By increasing or decreasing the muxing, the memory's aspect ratio can be altered to the user's advantage. Typically, this built in column mux is two, but may be higher depending on the memory. Another advantage is the sense amplifier's layout requirement. In the mux two case, the layout requirement has a pitch of two rather than one.
Unfortunately, a major disadvantage of the built in column mux is power consumption. Any time a row is selected, either read or write, one bit line from each memory cell accessed by that row will eventually discharge to ground. This occurs on all the memory cells accessed by the row, even the cells that are not of interest, i.e., the cells not being addressed by the column mux address. The bit lines, associated with the cells, that are discharged to ground require precharging "rail to rail" for the next clock cycle. As a result, in a column mux of two, power is wasted in that half the memory cells that are discharged are not of pending interest. Precharge power consumption is a significant percentage of overall power consumption.
FIG. 2 illustrates a typical memory architecture for a dual port memory. As in the single port memory shown in FIG. 1, the dual port memory suffers from the dissipation problem due to unselected columns being discharged. In addition, the dual port memory has a problem that exists during simultaneous row addressing. Any time either port selects a row address, the unselected column address with their associated unselected memory cells, discharge all unselected bit lines to ground. If the other port now selects one of these unselected memory cells to perform a write operation, the write speed will be degraded significantly since it must charge up the previously discharged bit line through a "weak" pass transistor of the opposite port in order to write to the cell, as shown in FIG. 3. A typical solution to this problem is to not disable the precharge circuitry on unselected columns. Unfortunately, the penalty is large power consumption.